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intel ? communications chipset 89xx series specification update october 2012 document number: 328000-001US
intel ? communications chipset 89xx series specification update october 2012 2 order number: 328000-001US legal lines and disclaimers information in this document is provided in connection with in tel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by th is document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent , copyright or other intellectual property right. unless otherwise agreed in writing by intel, the intel products are not designed nor intended for any application in which the failure of the intel product could create a situation where personal injury or death may occur. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the a bsence or characteristics of any features or instructions marked "res erved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the information here is subject to change without notic e. do not finalize a design with this information. the products described in this document may contain design defect s or errors known as errata which may cause the product to dev iate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature, may be obtained by calling 1-800-548- 4725, or go to: http://www.intel.com/#/en_us_01 intel processor numbers are not a measure of performance. processor numbers differentiate features within each processor family , not across different processor families. go to: http://www.intel.com/products/processor%5fnumber/ i2c is a two-wire communications bus/protocol developed by philip s. smbus is a subset of the i2c bus/protocol and was developed by intel. implementations of the i2c bus/protocol may require licenses fr om various entities, including philips electronics n.v. and nort h american philips corporation. intel and the intel logo are trademarks of intel corporation in the u.s. and/or other countries. *other names and brands may be claimed as the property of others. copyright ? 2012, intel corporation. all rights reserved.
intel ? communications chipset 89xx series october 2012 specification update order number: 328000-001US 3 contents?chipset 89xx series contents revision history .................................................................................................. 4 preface ...................................................................................................................... 5 affected documents/related documents .............. .................................................. 5 nomenclature ..................................................................................................... 5 summary tables of changes ...................................................................................... 6 codes used in summary tables............................................................................. 6 stepping ................................................................................................. 6 page....................................................................................................... 6 status .................................................................................................... 6 row ....................................................................................................... 6 identification information ....................................................................................... 11 component marking information ......................................................................... 11 device & revision identification .............................................................................. 12 errata ...................................................................................................................... 13 specification changes .............................................................................................. 36 specification clarifications ...................................................................................... 37 documentation changes .......................................................................................... 39
chipset 89xx series? intel ? communications chipset 89xx series specification update october 2012 4 order number: 328000-001US revision history date revision description october 2012 001 ? initial release
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 5 preface?chipset 89xx series preface this document is an update to the specific ations contained in the affected documents/ related documents table below. this document is a compilation of device and documentation errata, specification clarifications and changes. it is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. information types defined in nomenclature are consolidated into the specification update and are no longer published in other documents. this document may also contain information that was not previously published. affected documents/related documents nomenclature errata are design defects or errors. errata may cause the behavior of the pch to deviate from published specifications. hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present in all devices. specification changes are modifications to the current published specifications. these changes will be incorporated in any new release of the specification. specification clarifications describe a specification in greater detail or further highlight a specification?s impact to a complex design situation. these clarifications will be incorporated in any new release of the specification. documentation changes include typos, errors, or omissions from the current published specifications. these will be in corporated in any new release of the specification. document title document number/ location intel ? communications chipset 89xx series - datasheet 327879-00x
chipset 89xx series?summary tables of changes intel ? communications chipset 89xx series specification update october 2012 6 order number: 328000-001US summary tables of changes the following tables indicate the errata , specification changes, specification clarifications, or documentation changes which apply to the intel ? communications chipset 89xx series product. intel may fix so me of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. these tables uses the following notations: codes used in summary tables stepping x: errata exists in the stepping indicated. specification change or clarification that applies to this stepping. (no mark) or (blank box): this erratum is fixed in listed stepping or specification change does not apply to listed stepping. page (page): page location of item in this document. status doc: document change or update will be implemented. future fix: this erratum may be fixed in a future stepping of the product. fixed. this erratum has been previously fixed. no fix: there are no plans to fix this erratum. row change bar to left of table row indicates this erratum is either new or modified from the previous version of the document.
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 7 summary tables of changes?chipset 89xx series table 1. errata (sheet 1 of 3) erratum number stepping status errata c1 1 xno fix dmi port: dmi degradation mode not functional if lane reversal is implemented 2 xno fix pcie root port (rp): pcie rp degradation mode not functional if lane reversal is implemented 3 xno fix endpoint (ep): pcie ep does not check the pcie tlp digest (td) bit 4 xno fix gbe: gbe smgii protocol layer delays affects system collision detection 5 xno fix gbe: gbe mac may drop the first receive (rx) packet after a link speed change 6 xno fix pcie root port (rp): pcie rp degradation is not functional. 7 xno fix sata: sata low power device detection 8 xno fix usb: usb port stall with bulk and control traffic 9 xno fix sata: sata sync escape issue 10 xno fix usb: usb end of frame when retrying packets issue 11 xno fix usb: usb classic device removal issue 12 xno fix usb: usb rmh descriptor may report incorrect number of usb ports 13 xno fix pch: high precision event timer (hpet) writing timing issue 14 xno fix usb: usb full-speed port staggering 15 xno fix usb: usb devices may slow or hang 16 xno fix usb: usb low-speed control transactions 17 xno fix sata: sata controller may not detect unsolicited sata cominits 18 xno fix sata: sata hot unplug may not be detected 19 xno fix usb: usb missing ack 20 xno fix sata: sata 6 gb/s device detection 21 xno fix pcie root port (rp): pcie rp link disable bit 22 xno fix usb: usb isochronous in transfer error issue 23 xno fix usb: usb full-speed/low-sp eed device removal issue 24 xno fix usb: usb babble detected with software overscheduling 25 xno fix usb: usb low-speed/full-speed eop issue 26 xno fix usb: usb pll control fsm not getting reset on global reset 27 xno fix usb: usb asynchronous retries prioritized over periodic transfers 28 xno fix usb: incorrect data for low-speed or fu ll-speed usb periodic in transaction 29 xno fix usb: usb rmh delayed periodic traffic timeout issue 30 xno fix gbe: gbe mng reset clears resource grant with no feedback 31 xno fix gbe mdio: com_mdio and destination bits of mdicnfg register are not loaded consistently from eeprom 32 xno fix gbe mng: i2c data out hold time violation 33 xno fix gbe eeprom: ee_cs_n control signal hold time violation 34 xno fix gbe sgmii: counters incorrectly increment on collision 35 xno fix gbe tsync: auxiliary timestamp from sdp is unreliable 36 xno fix endpoint (ep): spurious msi/msix interrupt generated 37 xno fix endpoint (ep): pcie ep may not detect unexpected completion packets
chipset 89xx series?summary tables of changes intel ? communications chipset 89xx series specification update october 2012 8 order number: 328000-001US 38 xno fix gbe: gbe near end analog loopback not supported 39 xno fix pcie root port (rp): pcie rp may not au tomatically switch into compliance mode 40 xno fix endpoint (ep): pcie ep incorrect completion id 41 xno fix endpoint (ep): pcie ep link status register 2 (lnksts2) not implemented for functions[1-4] 42 xno fix endpoint (ep): pcie malformed packet checking is not implemented 43 xno fix endpoint (ep): pcie ep virtual functions wrongly reporting advisory errors as correctable errors 44 xno fix endpoint (ep): pcie ep sends two erro r messages to the host for io_rd to unsupported address space 45 xno fix endpoint (ep): pcie ep may generate spurious error message 46 xno fix endpoint (ep): pcie ep incorr ect handling of multiple errors 47 xno fix endpoint (ep): pcie ep incorrect ha ndling of poisoned memory writes. 48 xno fix endpoint (ep): pcie ep does not detect poisoned data for io_wr transactions 49 xno fix endpoint (ep): pcie ep does not reliabl y update the header log and first error pointer 50 xno fix endpoint (ep): pcie ep does not report the function number associated with a poisoned tlp error 51 xno fix endpoint (ep): pcie ep does not send er ror message for mmio read transaction to unsupported memory space 52 xno fix endpoint (ep): active state power management (aspm) not supported 53 xno fix endpoint(ep): incorrect logging & reporting of data link protocol errors (dlpes) 54 xno fix endpoint (ep): pcie ep transition from d3hot to l1 55 xno fix endpoint (ep): some pcie ep configuration registers have wrong attribute assignment 56 xno fix endpoint (ep): pcie ep transiti on from d3hot to d0uninitialized 57 xno fix endpoint (ep): pcie ep link control regist er 2 (plcntlr2) sticky bits not retaining value after hot reset 58 xno fix usb: pll configuration settings for usb-io interface 59 xno fix endpoint (ep): pcie transaction pending bit initialization 60 xno fix endpoint (ep): incorrect io transaction response in d3hot state 61 xno fix pch: ieee std. 1149.6 extest_pulse and extest_train instructions not supported by non-ep_jtag port. 62 xno fix pch: auxiliary (aux) and auxi liary2 (aux2) thermal trip interrupts not functional. 63 xno fix endpoint (ep): pcie ep does not report timeout errors 64 xno fix endpoint (ep): pcie ep does not register correctable errors 65 xno fix endpoint (ep): pcie ep incorrect handling of read completions with unsupported request (ur) status 66 xno fix endpoint (ep): pcie ep does not enable th e correct number of virtual functions (vfs) 67 xno fix gbe: sgmii interface receiver does not meet input differential hysteresis (vhyst) specification 68 xno fix sata: incorrect number of supported ports reported 69 xno fix endpoint (ep): pcie ep does not indicate poisoned data from reads of corrupted memory table 1. errata (sheet 2 of 3) erratum number stepping status errata c1
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 9 summary tables of changes?chipset 89xx series 70 xno fix endpoint (ep): pcie ep link may not train 71 xno fix gbe: sgmii interface transmit rise (t rise ) and fall (t fall ) ac timing specification violation 72 xno fix quickassist technology (qat ): decompression adler32 chec ksum may be calculated incorrectly 73 xno fix endpoint (ep): pcie ep link disable requires hot reset 74 xno fix gbe: gbe macs pci config space does not contain valid vid/did default values 75 xno fix gbe: gbe interface transmit volt age level specification violation 76 xno fix usb: usb full/low speed port reset or clear transaction translation (tt) buffer request 77 xno fix usb: usb rmh think time issue 78 xno fix usb: usb rmh false disconnect issue table 1. errata (sheet 3 of 3) erratum number stepping status errata c1
chipset 89xx series?summary tables of changes intel ? communications chipset 89xx series specification update october 2012 10 order number: 328000-001US table 2. specification changes number specification change none to report at this time. table 3. specification clarifications number specification clarification 1 gbe: use of wake on lan together with manageability 2 gbe smbus: illegal stop condition 3 gbe serdes: an_timeout only works when link partner idle table 4. documentation changes number documentation change none to report at this time.
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 11 identification information?chipset 89xx series identification information component marking information the intel ? communications chipset 89xx series pc h components are identified in the component markings in ta b l e 5 . table 5. component identification pch stepping mm# s-spec (grp1line1) product notes c1 923820 sljw2 dh8900cc - sku1 sku1: intel ? communications chipset 8900 923819 sljvz dh8903cc - sku2 sku2: intel ? communications chipset 8903 923818 sljvy dh8910cc - sku3 sku3: intel ? communications chipset 8910 923817 sljvx dh8920cc - sku4 sku4: intel ? communications chipset 8920 figure 1. top markings
chipset 89xx series?device & revision identification intel ? communications chipset 89xx series specification update october 2012 12 order number: 328000-001US device & revision identification the revision id (rid) is traditionally an 8-bi t register located at the offset 08h in the pci header of every pci device and function. the assigned value is based on the product stepping. table 6. intel ? communications chipse t 89xx series device and revision id table device function pch pcie devices device id (did) revision id (rid) comments b0:d28:fn 0x233e used by the pcie root port function that has subtractive decode compatibility set to '1'. b0:d31:f0 lpc 0x2310 0x08 lpc controller b0:d31:f2 sata 0x2323 0x08 sata controller #1 b0:d31:f3 smbus 0x2330 0x08 smbus host controller b0:d31:f5 sata 0x2326 0x08 sata controller #2 b0:d31:f6 thermal 0x2332 0x08 thermal subsystem b0:d31:f7 wdt 0x2360 0x08 wdt for core reset b0:d29:f0 usb 0x2334 0x08 usb gen 2 b0:d22:f0 intel ? mei #1 0x2364 0x08 intel ? management engine interface #1 b0:d22:f1 intel ? mei #2 0x2365 0x08 intel ? management engine interface #2 b0:d28:f0 pcie root port 1 0x2342 0x08 the pcie root port with a subtractive decode will have a different device id (see row 1 of this table). b0:d28:f1 pcie root port 2 0x2344 0x08 b0:d28:f2 pcie root port 3 0x2346 0x08 b0:d28:f3 pcie root port 4 0x2348 0x08 bm:d0:f0 pcie endpoint 0x0434 0x21 pcie endpoint an d quickassist technology (qat) bm:d0:f1 gbe mac 0 0x0436 0x21 the device id for the gbe controllers can be overwritten by the eeprom. bm:d0:f2 gbe mac 1 0x0436 0x21 bm:d0:f3 gbe mac 2 0x0436 0x21 bm:d0:f4 gbe mac 3 0x0436 0x21
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 13 errata?chipset 89xx series errata 1. dmi port: dmi degradation mode not functional if lane reversal is implemented problem: dmi degradation mode will not work wh en dmi lanes are routed in reverse order. implication: if the dmi port is routed with the lanes reversed, it will work in full-mode only. the interface will not work if a link problem o ccurs and causes the interface to degrade. workaround: do not route dmi lanes in reverse order. status: no fix. 2. pcie root port (rp): pc ie rp degradation mode not functional if lane reversal is implemented problem: pcie rp degradation mode will not work when the pcie lanes are routed in reverse order. implication: if the pcie rp is routed with the la nes reversed, it will work in full-mode only. the interface will not work if an error occu rs and causes the interface to degrade. workaround: do not route pcie rp lanes in reverse order. status: no fix 3. endpoint (ep): pcie ep does not check the pcie tlp digest (td) bit problem: the ep does not check the td bit (bit 7 of byte 2) in the pcie transaction layer packet (tlp) header. implication: if the ep receives a tlp with the td bit set, the following will happen: ? if the tlp contains the 4-byte digest fiel d, the ep will not complete the request and will incorrectly respond with a malformed packet completion. ? if the tlp does not contain the 4-byte dige st field, the ep will complete the request instead of responding with a malformed packet completion. workaround: ensure that the td bit in the tlp header is not set. status: no fix.
chipset 89xx series?errata intel ? communications chipset 89xx series specification update october 2012 14 order number: 328000-001US 4. gbe: gbe smgii protocol layer delays affects system collision detection problem: gbe sgmii protocol delays inhibits the proper detection of system collisions. implication: collision detection errors may cause transmission data corruption. workaround: reduce standard network transmission wire length by 10% to offset delays introduced by the smgii layer. status: no fix. 5. gbe: gbe mac may drop the first receive (rx) packet after a link speed change problem: the gbe mac internal clock synchronizat ion may not be complete before the sgmii link is established following a link speed change. this may result in the first receive (rx) packet immediately following the link speed change to be truncated in the mac layer and subsequently dropped due to bad frame check sequence (fcs). implication: the ethernet protocol fcs protects an y bad/incomplete packet that may have appeared in mac as an effect of this issue. dropped packet due to bad fcs may be recorded in statistics. workaround: none. status: no fix. 6. pcie root port (rp): pcie rp degradation is not functional. problem: the pcie rp cannot degrade from a x4 link to a x2 or x1 link. implication: if the rp is configured as pcie x4 port and a x2 or x1 device is connected, the link will not train and the device will not be seen. workaround: using the flash image configuration tool (fitc), configure soft strap 9 to bifurcate the root port as 4x1 or 1x4 as needed on the platform. status: no fix. 7. sata: sata low power device detection problem: the sata low power device detection (slpd) may not recognize, or may falsely detect, a sata hot-plug event during a partial or slumber link power management (lpm) state. implication: on systems that enable lpm, when a sa ta device attached to the pch is configured as external or hot-plug capable, one of the following symptoms may occur: ? symptom #1: a hot-plug or external sata device removal which is not detected results in the os and intel ? matrix storage manager or intel ? rapid storage technology console falsely reporting the de vice present, or incorrectly identifying an esata device. ? symptom#2: a false hot-plug removal detection may occur resulting in os boot hang or odd media playback hang. workaround: a software driver workaround is implemented. status: no fix.
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 15 errata?chipset 89xx series 8. usb: usb port stall with bulk and control traffic problem: when a single usb bulk device is acti ve on an ehci controller, and the device has pending control and bulk traffic, the usb controller may not be able to resolve which traffic type is a priority and the association with the device may stall. the processor must be in c0 for an extended period of time, such as when cx states are disabled, or if system traffic prevents the system from leaving c0. implication: the usb device may appear unresponsiv e. if cx states are enabled, the device may recover a short time later. note: intel has only observed this failure on a limited number of devices. failure only occurs if software associated with a usb device programs the nak count reload bits defined in the ehci specification for usb rev 1.0 to 0. workaround: bios implementation follows intel ? communications chipset 89xx series bios specification and program d29:f0:88h[7] = ?1b ? . status: no fix. 9. sata: sata sync escape issue problem: when sync escape by a sata device occurs on a d2h fis, the chipset 89xx series does not set the pxis.ifs bit to ?1.? this deviates from section 6.1.9 of the rev 1.3 serial ata advanced host controller interface (ahci). implication: there is no known observable impact. instead of detecting the ifs bit, software will detect a timeout error caused by the sync escape and then respond. workaround: none. status: no fix. 10. usb: usb end of frame when retrying packets issue problem: if the usb controller encounters a full-sp eed or low-speed usb transaction with errors, it may retry the transaction without considering if the transaction can finish before the end of the current frame. implication: the implication depends on the particul ar usb device. the usb controller will attempt to recover per error handling specified in section 4.5.2 of the usb specification 2.0. the device may hang and require cycle to resume normal functionality. note: intel has only observed this behavior on a limited number of usb devices. the implication only occurs if a usb device does not correctly respond to error handling as specified in sectio n 4.5.2 of the usb specification 2.0. workaround: none. status: no fix.
chipset 89xx series?errata intel ? communications chipset 89xx series specification update october 2012 16 order number: 328000-001US 11. usb: usb classic device removal issue problem: if two or more usb full-speed / low-speed devices are connected to the same usb controller, and if the devices are not suspende d, then if one device is removed, one or more of the devices remaining in the sy stem may be affected by the disconnect. implication: the implication is device-dependent. a device may experience a delayed transaction, stall, and be recovered via software, or it may stall and require a reset such as a hot-plug to resume normal functionality. workaround: none. status: no fix. 12. usb: usb rmh descriptor may repo rt incorrect number of usb ports problem: the pch supports 6 ports on rmh #1 and may incorrectly report 8 usb ports in the bnbrports field of the rmh hub descriptor. implication: if ac power is removed while the syst em is in hibernate, when the system resumes , new usb devices may not be detected, and all devices on rmh #1 may not function. note: ac power removal while the system is in hibernate is not a normal usage model, or common occurrence. workaround: none. status: no fix. 13. pch: high precision event time r (hpet) writing timing issue problem: a read transaction that immediately follows a write transaction to the hpet register space may return an incorrect value. implication: implication depends on the usage model as noted below: ? for the hpet timn_comp timer 0 co mparator value register and hpet main_cnt?main counter value register, the issue could result in the software receiving stale data. this may result in undetermined system behavior. note: timers [1:7] are not affected by this issue. ? for timern_val_set_cnf bit 6 in the ti mn_conf?timer n configuration, there is no known usage model for reading this bit and there are no known functional implications. ? a write to the high precision timer configuration (hptc) register followed by a read to hpet register space, may return all 0xffff_ffffh. workaround: software workaround has be en identified as described below: ? a write to the hpet timn_comp timer 0 comparator value register should be followed by two reads that are discarded, and a third read where the data can be used. ? a write to the hpet main_cnt - main counter register should be followed by one read that is discarded, and a second read where the data can be used. workaround: timern_val_set_cnf bit 6 in the timn_conf - timer n - there is no known usage model to read this bit, but a write to the bit should be followed by one read that is discarded and a second read where the data can be used. status: no fix.
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 17 errata?chipset 89xx series 14. usb: usb full-speed port staggering problem: when usb full-speed/low-speed port stag gering is enabled, the usb controller may not wait for the bus to return to an idle st ate after an end of pa cket (eop), and may incorrectly acknowledge bus noise as a data packet. implication: some full-speed/low-speed devices may fail to enumerate and function. note: this issue has been seen with a minimum number of devices on some motherboard ports with certain cable and trace lengths. workaround: bios should disable usb fs/ls po rt staggering by clearing rcba+3564h[12]. status: no fix. 15. usb: usb devices may slow or hang problem: when the processor is in c0, and a sing le bulk high-speed usb device is active, the port associated with the active device may hang. implication: the implication is device driver-dep endent. intel has observed some usb devices may have decreased performance, or the device may hang. workaround: bios implementation follows intel ? communications chipset 89xx series bios specification (section 16.9) and programs d29:f0:88h[7]= ? 1b ? . status: no fix. 16. usb: usb low-speed control transactions problem: if the usb control buffers in the pch ra te matching hub(s) are saturated with pending transactions, the buffers may not be serviced in round robin order. implication: some low-speed endpoints may not receive their pending control transactions. note: this issue has only been observed in a synthetic test environment. the implication will be device, driver , and operating system specific. workaround: none. status: no fix. 17. sata: sata controller may not detect unsolicited sata cominits problem: sata controller may not detect an unsolicited cominit from a sata device. implication: the sata device may not be properly detected and configured, resulting in the device not functioning as expected. workaround: bios implementation follows intel ? communications chipset 89xx series bios specification and programs d31:f2:offset 98h[20:19] = ?11b?. status: no fix. 18. sata: sata hot unplug may not be detected problem: sata controller may not detect the unpl ug of a sata 3.0 gb/s device on a hot-plug enabled sata port. implication: the unplugged sata device may temporarily appear to be available. workaround: bios should program d31:f2:offset 98h[6:5] = ?00b? . status: no fix.
chipset 89xx series?errata intel ? communications chipset 89xx series specification update october 2012 18 order number: 328000-001US 19. usb: usb missing ack problem: following system power cycling or s3-s 5 resume, if both high-speed and low-speed/ full-speed devices are attached to the same controller, the host controller may not respond to a high-speed device ack during a get descriptor request from the host software to a usb high-speed port. implication: usb high-speed devices may not be de tected after a power cycling or s3-s5 resume. ? intel has only observed this failure on a limited number of platforms. on a failing platform, the issue occurs infrequently. ? full-speed and low-speed usb devices are not impacted by this issue. workaround: none. status: no fix. 20. sata: sata 6 gb/s device detection problem: the sata controller may not be able to complete sata out of band (oob) signaling with sata 6gb/s devices and down-shift to sata 3 gb/s speed. implication: sata controller may not detect a sata 6 gb/s device upon power up or resume from s3, s4 or s5 state, resulting in indeterminate system behavior. workaround: none. status: no fix. 21. pcie root port (rp): pcie rp link disable bit problem: the pcie rp may not exit the disable state when the link control register ?link disable? bit is set and pcie device electrical idle exit is detected. implication: port-specific software-directed hot pl ug or power management (pm) support using the ?link disable? bit may cause pcie rp to be stuck in the ?link disable state? until a host reset with power cycling occurs. workaround: for pcie rp port-specific software-directed hot plug or power management support, use the pci power management control register d3hot bits instead of the link disable bit. status: no fix. 22. usb: usb isochronous in transfer error issue problem: if a usb full-speed inbound isochronous transaction with a packet length 190 bytes or greater is started near the end of a micro-frame, the usb controller may see more than 189 bytes in the next micro-frame. implication: if the usb controller sees more than 189 bytes for a micro-frame, an error will be sent to software and the isochronous transfer will be lost. if a single data packet is lost, no perceptible impact for the end user is expected. note: intel has only observed the issue in a synthetic test environment where precise control of packet scheduling is available, and has not observed this failure in its compatibility validation testing. ? isochronous traffic is periodic and cannot be retried, thus it is considered good practice for software to schedule isochronous transactions to start at the beginning of a micro-frame. known software solutions follow this practice.
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 19 errata?chipset 89xx series ? to sensitize the system to the issue, additional traffic such as other isochronous transactions or retries of asynchronous tr ansactions would be required to push the inbound isochronous transaction to the end of the micro-frame. workaround: none. status: no fix. 23. usb: usb full-speed/low-speed device removal issue problem: if two or more usb full-speed/low-speed devices are connected to the same usb controller, the devices are not suspended, and one device is removed, one or more of the devices remaining in the system may be affected by the disconnect. implication: the implication is device-dependent. a device may experience a delayed transaction, stall, and be recovered via software, or it may stall and require a reset such as a hot-plug to resume normal functionality. workaround: none. status: no fix. 24. usb: usb babble detected wi th software overscheduling problem: if software violates usb periodic sched uling rules for full-speed isochronous traffic by overscheduling, the rmh may not handle th e error condition properly and return a completion split with more data than the length expected. implication: if the rmh returns more data than ex pected, the endpoint will detect packet babble for that transaction, and the packet will be dropped. since overscheduling occurred to create the error condition, the packet woul d be dropped regardless of rmh behavior. if a single isochronous data packet is lost, no perceptible impact to the end user is expected. note: usb software overscheduling occurs when the amount of data scheduled for a micro-frame exceeds the maximum budget. this is an error condition that violates the usb periodic scheduling rule. note: this failure has only been recreated synthetically with usb software intentionally overscheduling traffic to hit the error condition. workaround: none. status: no fix. 25. usb: usb low-speed/full-speed eop issue problem: if the eop of the last packet in a us b isochronous split transaction (defined as a transaction > 189 bytes) is dropped or delayed 3 ms or longer, the following may occur: ? if there are no other pending low-speed or full-speed transactions, the rmh will not send sof, or keep-alive. devices connected to the rmh will interpret this condition as idle and will enter suspend. ? if there are other pending low-speed or full-speed transactions, the rmh will drop the isochronous transaction and resume normal operation. implication: ? if there are no other transactions pending, the rmh is unaware a device has entered suspend and may start sending a transaction without waking the device.
chipset 89xx series?errata intel ? communications chipset 89xx series specification update october 2012 20 order number: 328000-001US the implication is device-dependent, but a device may stall and require a reset to resume functionality. ? if there are other transactions present, only the initial isochronous transaction may be lost. the loss of a single isochronous transaction may not result in end user perceptible impact. note: intel has only observed this failure when using software that does not comply with the usb specification and violates the hardware isochronous scheduling threshold by terminating transactions that are already in progress. workaround: none. status: no fix. 26. usb: usb pll control fsm not getting reset on global reset problem: the usb pll may not lock if a global re set occurs early during a cold boot sequence. implication: the usb port would not be functional and additional cold boot would be necessary to recover. workaround: none. status: no fix. 27. usb: usb asynchronous retries pr ioritized over periodic transfers problem: the integrated usb rmh incorrectly prioritizes lo w-speed and full-speed asynchronous retries over dispatchable periodic transfers. implication: periodic transfers may be delayed or aborted. if the asynchronous retry latency causes the periodic transfer to be aborted, the impact varies depending on the nature of periodic transfer: ? if a periodic interrupt transfer is aborte d, the data may be recovered by the next instance of the interrupt or the data could be dropped. ? if a periodic isochronous transfer is abor ted, the data will be dropped. a single dropped periodic transaction should not be noticeable by the end user. note: this issue has only been seen in a synthetic environment. the usb spec does not consider the occasional loss of periodic traffic a violation. workaround: none. status: no fix. 28. usb: incorrect data for low-spee d or full-speed usb periodic in transaction problem: the periodic frame list entry in dram for a usb low-speed or full-speed periodic in transaction may incorrectly get some of its data from a prior periodic in transaction which was initiated very late into the preceding micro-frame. it is considered good practice for software to schedule periodic transactions at the start of a micro-frame. however periodic transactions may occur late into a micro-frame due to the following cases: ? asynchronous transaction starting near the end of the proceeding micro-frame gets asynchronously retried.
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 21 errata?chipset 89xx series note: transactions getting asynchronous retried would only occur for ill-behaved usb device or usb port with a signal integrity issue. ? two periodic transactions are scheduled by software to occur in the same micro-frame and the first one needs to push the second periodic in transaction to the end of the micro-frame boundary implication: the implication will be device, driver, or operating system specific. note: this issue has only been observed in a synthetic test environment. workaround: none. status: no fix. 29. usb: usb rmh delayed peri odic traffic timeout issue problem: if an interrupt transaction is pu shed to the x+4 micro-frame boundary due to asynchronous retries, the rmh may not wait for the interrupt transaction to time out before starting the next transaction. if rmh transaction translator (tt) reaches a discard boundary, a timeout may be ignored. implication: if the next transaction is intended fo r the same device targeted by the interrupt, the successful completion of that transaction is device dependent and cannot be guaranteed. the implication may differ depe nding on the nature of the transaction: (this only impacts tt ? low-speed / full-speed). ? if the transaction is asynchronous and the device does not respond, it will eventually be retried with no impact. ? if the transaction is periodic and the devi ce does not respond, the transfer may be dropped. a single dropped periodic transact ion should not be noticeable by the end user. note: this issue has only been seen in a synthetic environment. workaround: none. status: no fix. 30. gbe: gbe mng reset clears re source grant with no feedback problem: when accessing the eeprom (via eec register), grants may be lost due to deadlock or firmware reset. software will not be notified of the lost grant. a driver in the middle of a bit bang may renew the request and rece ive the grant without knowing that it is actually starting a new transaction. implication: 1. eec bit banging transactions may fail. 2. long transactions may turn into different transactions than expected. workaround: 1. software should not execute bit bang sequences longer than one word at a time. 2. when software reads the eec, it should make sure that it still has the request and grant. if not, software should renew it and re-start the transaction. this does not cover all cases but reduces the possibility of a problem. status: no fix.
chipset 89xx series?errata intel ? communications chipset 89xx series specification update october 2012 22 order number: 328000-001US 31. gbe mdio: com_mdio and destinat ion bits of mdicnfg register are not loaded consistently from eeprom problem: the com_mdio (bit 30) and destinat ion (bit 31) bits of the mdicnfg register (0x0e04) are not loaded consistently from the eeprom. in some cases, the hardware default value of 0b is used instead. implication: software that relies on the eeprom-loaded value might not be able to initialize an external phy. workaround: software should assume that the initia l values of these bits are undefined and should program them before attempting to initializ e an external phy. the eeprom bits can be used to determine the intended settings. note: a gbe driver workaround has been identified and deployed for intel drivers. status: no fix. 32. gbe mng: i2c data out hold time violation problem: the gbe mng i2c interface should provide a data out hold time of 50 ns on the sfpx_i2c_data pins. the actual hold time is about 16 ns. implication: i2c timing specification violation. ther e have been no reports of failures resulting from this timing. note that the data input hold time required is zero, so the provided output hold time should be more than enough as long as the i2c clk and data signals are reasonably matched on the board. workaround: none. status: no fix. 33. gbe eeprom: ee_cs_n control signal hold time violation problem: the eeprom datasheet indicates a hold time of 250 ns for ee_cs_n relative to the falling edge of ee_sk (tcsh). at the end of a read or rdsr operation, ee_cs_n is actually negated about 32 ns af ter the falling edge of ee_sk. implication: although this is a timing specification violation for many eeprom devices, no malfunction has been reported. workaround: none. status: no fix. 34. gbe sgmii: counters inco rrectly increment on collision problem: in sgmii mode/half duplex, the statis tics counters listed below incorrectly increment when a collision occurs: name definition location rlec length error counter 0x4040 crcerrs crc error counter 0x4000 rfc receive frame counter 0x40a8 implication: error counters may not be accurate. workaround: none. status: no fix.
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 23 errata?chipset 89xx series 35. gbe tsync: auxiliary time stamp from sdp is unreliable problem: the sdp inputs to the timestamp logic ar e not properly synchronized. as a result, both the auxiliary timestamp register values and the auxiliary timestamp taken bits in tsauxc are sometimes loaded incorrectly. implication: the auxiliary timestamp feat ure should be considered unreliable. workaround: for applications that use the auxiliary timestamp feature to synchronize to an external clock, it might be acceptable to drop so me of the samples. for such applications, software can filter out many of the incorre ct timestamp values by comparing them to an approximate expected timestamp and discarding unreasonable values. in addition, the following method can be used to filter out incorrect values: ? connect the input signal to two sdp inputs for the same port. ? using the tssdp register, assign one of the sdp inputs to au x0 and the other sdp input to aux1. ? when reading the tsauxc register to check for new samples, check that both autt0 and autt1 are set. otherwise, discard the sample. ? read both the aux0 and aux1 timestamp values and compare the values. discard the values if they differ by more than the sampling uncertainty of 8 ns (if the sdp inputs are balanced externally) or slightly higher if the external trace lengths differ significantly. using this method, along with a software filter for expected values, almost all errors can be filtered out, with the remaining samp les having a very high probability of being correct. when using port 0, the following combinatio ns of sdp connections to aux0 and aux1 allow the above method to filter out all errors. aux0 aux1 connection connection sdp0 sdp1 sdp0 sdp3 sdp1 sdp0 sdp1 sdp2 sdp2 sdp0 sdp2 sdp1 sdp2 sdp3 sdp3 sdp2 status: no fix. 36. endpoint (ep): spurious ms i/msix interrupt generated problem: when binding an interrupt from the default interrupt core (core 0) to the associated interrupt core, extra interrupts may be generated when clearing the pci_msix_entry_vector_ctrl during an active interrupt session. implication: extra interrupts may be generated during interrupt core binding. workaround: device driver workaround has been identified and deployed to handle the extra interrupts. status: no fix
chipset 89xx series?errata intel ? communications chipset 89xx series specification update october 2012 24 order number: 328000-001US 37. endpoint (ep): pcie ep may no t detect unexpect ed completion packets problem: the pcie ep may drop packets with unexpected completions if the unexpected completion packets are received back-to-back. implication: unexpected completion armored packets may not be detected and logged. workaround: none. status: no fix. 38. gbe: gbe near end analog loopback not supported problem: the gbe near end analog loopback is not supported by the pch gbe interface. implication: gbe near end analog loopback is not supported for debug purposes. workaround: none. status: no fix. 39. pcie root port (rp): pcie rp may not automatically switch into compliance mode problem: the pcie rp may not automatically swit ch into compliance mode when the transmitter is terminated to 50-ohm test load. implication: affects compliance testing. workaround: software configuration may be used to force the link to enter compliance mode in both components of the link and then initiate a hot reset on the link. status: no fix. 40. endpoint (ep): pcie ep incorrect completion id problem: the bus number (b) section within a comp letion id (b:d:f) sent to the host by the pcie ep is always set to ?0? for any co mpletion response. th e device and function numbers (d:f) sections are set correctly. implication: violation of pcie specification for ty pe 0 configuration write requests where functions are required to capture the bus number in the completion id of the response. workaround: none. status: no fix. 41. endpoint (ep): pcie ep link status register 2 (lnksts2) not implemented for functions[1-4] problem: the pcie lnksts2 register in ep func tions[1-4] is not implemented. reading the registers via functions[1-4] returns indeterminate values implication: the lnksts2 register cannot be read via functions[1-4]. workaround: read the lnksts2 register via function 0. status: no fix.
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 25 errata?chipset 89xx series 42. endpoint (ep): pcie malformed pa cket checking is not implemented problem: a malformed pcie tlp (transaction layer packet) is a tlp that violates specific tlp formation rules as defined in the pci expr ess base specification revision 2.0 dated december 20, 2006. the pcie endpoint does not implement checks for malformed tlps, and thus no malformed tlp errors will be reported by the device. the pcie endpoint does not transmit malformed tlps. implication: reception of the following types of malformed tlps by the pcie endpoint may cause silent data corruption: ? the size of the data payload of a receiv ed tlp as given by the tlp's length field exceeds the length specified by the value in the max_payload_size field of the pcie endpoint (sec 2.2.2 of pcie base spec). ? the value in the tlp's length field does not match the actual amount of data included in the tlp (sec 2.2.2, sec 2.2.9 of pcie base spec). ? a tlp where the tlp digest (td) bit value does not correspond with the observed size (accounting for the data payload, if present), (sec 2.2.3 of pcie base spec). ? all received tlps which use undefined type field values (sec 2.3 of pcie base spec). workaround: as of october 2011 there were no pub lished malformed errata/sightings that did not have a workaround for all root ports or downstream ports listed below that would allow a malformed formed packet to be sent to the endpoint: pcie endpoint directly connected to any of the pcie root ports in these platforms ? sandy bridge en/ep + patsburg pch ? sandy bridge en/ep + chipset 89xx series pch ? sandy bridge gladden + chipset 89xx series pch ? sandy bridge desktop + cougar point pch ? ivy bridge en/ep + patsburg pch ? ivy bridge gladden + chipset 89xx series pch ? ivy bridge desktop + panther point pch ? jasper forest + ibexpeak pch ? nehalem + tylersburg ioh + ich10 ? westmere + tylersburg ioh + ich10 pcie endpoint directly connected to a downstream port of the following pcie switches: ? plx 87* family ? idt idt89hpes32nt24ag2 switch status: no fix
chipset 89xx series?errata intel ? communications chipset 89xx series specification update october 2012 26 order number: 328000-001US 43. endpoint (ep): pcie ep virtual fu nctions wrongly reporting advisory errors as correctable errors problem: the ep wrongly report advisory non-fatal errors as correctable errors (err_cor_messages) instead of as non-fatal errors (err_nonfatal messages). implication: system software should handle these advisory errors as non-fatal errors. workaround: none status: no fix 44. endpoint (ep): pcie ep sends tw o error messages to the host for io_rd to unsuppor ted address space problem: when an unsupported request is detected with an io_rd, the pcie ep may return two error messages to the host. implication: induces multiple handling for the same error. workaround: software should avoid io _rd to unsupported address space status: no fix 45. endpoint (ep): pcie ep may generate spurious error message problem: when clearing an error status bit while handling an error, the pcie endpoint may spuriously generate another e rror message for the same error. implication: system software may be invoked for an error that has already been handled. workaround: none status: no fix 46. endpoint (ep): pcie ep incorr ect handling of multiple errors problem: if a function has a pending error whic h has not yet been handled and cleared, and a second error is detected by another function, the ep does not report the second error. implication: if the second error is an uncorrectable error, it goes undetected and may affect system operation. workaround: none status: no fix. 47. endpoint (ep): pcie ep incorr ect handling of poisoned memory writes. problem: the ep is supposed to handle a poison ed memory write as an unsupported request and abort the request, but the ep completes the write to the final destination with the poisoned data, and reports an error. implication: may cause unpredictable behavior if the writes target control structures. workaround: none status: no fix
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 27 errata?chipset 89xx series 48. endpoint (ep): pcie ep does not detect poisoned data for io_wr transactions problem: io_wr transactions with poisoned data completes successfully without detection. implication: target registers may be corrupted. workaround: software should perform a read af ter a write to verify the register value status: no fix 49. endpoint (ep): pcie ep does not reliably upda te the header log and first error pointer problem: the header log and first error pointer ar e required to be updated for masked errors. if an unmasked error occurs after a masked error was detected, the header log and first error pointer are not be updated with the masked error information. implication: system software is unable to determin e the pcie transaction that caused the error. workaround: none status: no fix 50. endpoint (ep): pcie ep does not report the function number associated with a poisoned tlp error problem: the pcie ep reports poisoned tlp erro r using function number 0 regardless of the function that received the poisoned transaction. implication: wrong error source indicator for errors not associate with function 0. workaround: system software must scan all the pcie ep functions to identify the error status: no fix 51. endpoint (ep): pcie ep does not send error message for mmio read transaction to unsupp orted memory space problem: the pcie ep does not send an erro r message for mmio read access to unsupported memory space even though it indicates th e error in the error status register and completes the read request with unsupported request status. implication: none workaround: system software should not access unsupported memory space status: no fix
chipset 89xx series?errata intel ? communications chipset 89xx series specification update october 2012 28 order number: 328000-001US 52. endpoint (ep): active state power management (aspm) not supported problem: the pcie ep does not support active state link power management. implication: if active state power management is enabled and the link enters l0s, the ep may not re-enter l0. this will cause the system to hang. workaround: disable active state power management. status: no fix 53. endpoint(ep): incorrect logging & reporting of data link protocol errors (dlpes) problem: the pcie specification requires that non function-specific dlpes should be logged by all functions in the device which are configured to log the error, and should be reported by by the configured functions. however, at th e ep, only the last active function (last function which received a config transaction) reports the error. implication: violation of pcie specification for dlpe error reporting workaround: none status: no fix 54. endpoint (ep): pcie ep tr ansition from d3hot to l1 problem: if a mem_rd or io_wr request is received when the ep is in d3hot state with the link in l1, the ep appropriately transitions to l0 and reponds to the request as unsupported request (ur). however, the link fails to transition back to the l1 state after the completion and stays in l0 state. implication: violation of pcie power management specifications. workaround: none status: no fix 55. endpoint (ep): some pcie ep co nfiguration registers have wrong attribute assignment problem: some ep configuration registers have been wrongly assigned with read/write-once- sticky (rwos) access attributes instead of read-only (ro) attributes. the incorrect attribute affect the following physical and virtual function (pf/vf) registers: ? pcc - pf class code register ? psvid - pf subsystem vendor id ? psid - pf subsystem id register ? plcapr[0:3] - pf link capabilities register ? plsr[0:3] - pf link status register ? psriovfdid - pf sriov vf device id ? vcc[0:15] - vf class code register ? vsid[0:15] - vf subsystem id register implication: may fail pcie compliance tests. workaround: none status: no fix
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 29 errata?chipset 89xx series 56. endpoint (ep): pcie ep transiti on from d3hot to d0uninitialized problem: when the ep responds to a pcie transi tion from d0uninitialized to d3hot, the link appropriately transitions from l0 to l1. however, when the ep is transitioned back from d3hot to d0uninitialized, the link transitions from l1-to-l0-to-l1, instead of l1-to-l0. implication: violation of pcie power management specifications. workaround: perform the transition through d0 active (d0unitialized-to-d0active-to-d3hot). status: no fix 57. endpoint (ep): pcie ep link contro l register 2 (plcntlr2) sticky bits not retaining value after hot reset problem: the ep pcie configuration space plcntlr2 register (configuration: offset 0xa4) bits with read-write-sticky (rws) attributes are reset to ?0b? after hot reset. implication: functions that require the bits to remain sticky are impacted. for example, it impacts system compliance testing. workaround: none. status: no fix 58. usb: pll configuration se ttings for usb-io interface problem: for pch b0 stepping, the power-up de fault clock phase may cause transmit clock timing violations. implication: the usb transmitter may not function properly if the appropriate clock phase is not selected. workaround: bios workaround has been identifi ed and should be implemented as follows: ? bios should program usbir, bit[31] = ?1b?; ? bios should program pllctl2.u2txpsel (rcba, offset 0x356c), bits[31:29] = 0x3. ? bios should program usbir, bit[31] = ?0b? status: no fix 59. endpoint (ep): pcie transact ion pending bit initialization problem: the transaction pending bit in the pcie st atus register (ppdstat.tp) indicates that the pcie function has pending non-posted re quests awaiting completions. the pcie specification requires the bit be cleared when all pending requests have completed successfully or completed with a timeout. at the ep, the bit is cleared only for transactions that complete successfully; it is not cleared if the pending transaction complete with a timeout. implication: the transaction pending bit is one of the resources that software uses to quiesce a function prior to issuing a function level reset (flr) workaround: none. status: no fix
chipset 89xx series?errata intel ? communications chipset 89xx series specification update october 2012 30 order number: 328000-001US 60. endpoint (ep): incorrect io tran saction response in d3hot state problem: the ep responds normally to all io transa ctions when in d3hot state, as if in d0 state, instead of responding with unsurpported request (ur). implication: violation of pcie specifications. workaround: avoid io transactions when ep is in d3hot state. status: no fix 61. pch: ieee std. 1149.6 extest_pulse and extest_train instructions not supporte d by non-ep_jtag port. problem: the pch contains two separate jtag (tap) ports. one is used by the non-endpoint section on the pch (jtag) and the second is for the endpoint section on the pch (ep_jtag). both jtag ports are compatible with the ieee std. 1149.1; but only the ep_jtag is compatible with ieee std. 1149.6 instructions set. the non-ep jtag(jtag), which connects to the dmi/sata/pcie (root)/usb legacy i/o interfaces, is not compatible with the ieee std. 1149.6 and does not support the extest_pulse and extest_train instructions. implication: ieee std.1149.6 instruction set not supported by the non-ep jtag port workaround: none. status: no fix 62. pch: auxiliary (aux) and auxiliary 2 (aux2) thermal trip interrupts not functional. problem: the generation of pci interrupts on aux and aux2 thermal trip points in the thermal sensors (ts0 & ts1) do not work properly. implication: thermal interrupts are limited to catastrophic and hot state only. workaround: bios should disable the generation of interrupts on aux and aux2 thermal trips (ts0pien/ts1pien; tbarb + 0x82/0xc2) as follows: ? bios should program ts0pien/ts1pien, bit[0,3,4,7] = ?0b?. status: no fix 63. endpoint (ep): pcie ep do es not report timeout errors problem: when the pcie endpoint transaction timer expires, an error message is not sent to the host. however, all the relevant error status bits are updated correctly. implication: results in incomplete transaction which may cause the device to hang. workaround: device driver should implement a time out mechanism to detect device hang condition. this timeout mechanism can then be used by the software to intervene and reset the device status: no fix
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 31 errata?chipset 89xx series 64. e ndpoint (ep): pcie ep does no t register correctable errors problem: when the pcie ep receives and detects a receiver error it does not set the correctable error detected (ced) bit in the pf pcie device status register (ppdstat[0]). however, a correctable error message is sent to the host and the receiver error bit (res) is set in the pf pcie aer correctable error register (ppaercs[0]). implication: violation of system error reporting. note: since the pcie ep supports aer features, the device driver can use the aer correctable error status register to identify the cause of the correctable error message. workaround: none status: no fix 65. endpoint (ep): pcie ep incorrect handling of read completions with unsupported request (ur) status problem: when the pcie endpoint receives a read co mpletion with ur status it does not indicate the ur condition to the requester of the re ad. the requester may wait indefinitely for the completion of the transaction which can cause io requests back-up at the device. implication: the transaction incompletion may cause the device and system to hang. workaround: device driver should implement a time out mechanism to detect device hang condition. this timeout mechanism can then be used by the software to intervene and reset the device. status: no fix 66. endpoint (ep): pcie ep does not enable the correct number of virtual functions (vfs) problem: the numvf field of pf sriov number of vfs register (psriovnumvf), (bm:d0:f0; offset 150h - 153h, bits[15:0]) allows software to define the number of vfs assigned to a physical function (pf) as part of the process of creating vfs. programming the numvf field does not enable the correct number of vfs as expected. the actual number of enabled and expected vfs as shown as follows: numvf actual # of vfs enabled expected # of vfs 0x00 0 0 0x01 2 1 0x02 3 2 0x03 4 3 0x04 5 4 0x05 6 5 0x06 7 6 0x07 8 7 ---- ---- ---- 0x0f 16 15 0x10 undefined 16 implication: inhibits the capability to enable only 1 vf. provides capability to enable 2-16 vfs. workaround: none status: no fix
chipset 89xx series?errata intel ? communications chipset 89xx series specification update october 2012 32 order number: 328000-001US 67. gbe: sgmii interface receiver do es not meet input differential hysteresis (vhyst) specification problem: the sgmii specification requires the rece iver to ignore signals below 25 mv hysteresis voltage. however, the receiver may change states on input voltages close the 25 mv hysteresis specification which may cause unwanted state changes with non-monotonic input signals implication: although this is a specification violatio n, it does not affect the functional operation of the interface. workaround: none. status: no fix 68. sata: incorrect number of supported ports reported problem: the sata ahci host capabilities regist er is configured to indicate that the sata controller supports 4 ports (b0:d31:f2: ab ar + 00h, bit[4:0] = ?03h?). the number of supported ports in the register (nps) should have been set to ?01h? to indicate support for 2 ports. implication: incorrect reporting of supported ports. all pch skus support only two ports. workaround: driver should ignore the setting in the cap register, but instead to use the bios configuration of the ?active ports? in th e ports implemented register (b0:d31:f2: abar + 0ch, bit[5:4]). status: no fix 69. endpoint (ep): pcie ep does not indicate poisoned data from reads of corrupted memory problem: the ep fails to set the poisoned data bi t (ep bit) in the completion header for memory reads with corrupted data. implication: minimal impact because ia software is notified via interrupts when internal errors are detected. workaround: none. status: no fix 70. endpoint (ep): pcie ep link may not train problem: the default mux setting selects the wrong analog detect signal which may cause the internal state machines to get out of sync. implication: if the state machines get out of sync, the link will not train. workaround: this issue can be fixed with an eeprom image upgrade. ? using the intel starter images: ? the eeprom version = 3.0 or higher, includes the workaround. or ? if you build your own image with eict, include ?lan0-csr_auto_config_power_up_ptr_0 x27-csr-bottom_c.txt? version2 or higher in the eict pointer field ?lan0 > lan0 csr auto config power up ptr?. note: jntel recommends that the latest eeprom version (version 3.0 or higher) should be used status: no fix
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 33 errata?chipset 89xx series 71. gbe: sgmii interface transmit rise (t rise ) and fall (t fall ) ac timing specification violation problem: the sgmii interface transmit rise (t rise ) and fall (t fall ) times do not meet the sgmii ac timing specification ? the expected specification timing for t rise and t fall is 100 psec (min) and 200 psec (max) for 20% - 80% voltage rise or fall. ? the measured pch sgmii interface timing is 85 psec for 20% - 80% voltage rise or fall . implication: although this is a specification violatio n, it does not affect the functional operation of the interface. workaround: none. status: no fix 72. quickassist technology (qat): decompression ad ler32 checksum may be calculated incorrectly problem: decompression checksum computed for adler32 requests may produce erroneous results . implication: may cause valid decompression packets to be discarded . workaround: software should be tasked to ca lculate the checksum for adler32 requests. note: refer to issue# ixa00378662 in the intel? communications chipset 89xx series software - release notes (doc# 441779) for software solution. status: no fix 73. endpoint (ep): pcie ep link disable requires hot reset problem: the ep does not perform an internal upstream port reset on pcie link disable as required by the pci express specification . implication: if link disable is performed the credit cons umed counters are not reset, once the link re- trains the device will hang due to lack of available credits . workaround: after clearing the link disable bit in the ro ot or switch downstream port connected to the pch, a hot reset must be performed by setting the secondary bus reset bit of the bridge control register associated with the same root or switch downstream port . status: no fix
chipset 89xx series?errata intel ? communications chipset 89xx series specification update october 2012 34 order number: 328000-001US 74. gbe: gbe macs pci config spac e does not contain valid vid/did default values problem: the gbe macs do not have valid vid/did defa ult values in the pci configuration space for the pch c0 & c1 steppings . implication: if an eeprom with a valid image is not loaded during power-up or system reset, then the gbe macs vid and did may be randomly set and invalid . note: it is a mandatory requirement to have a pr e-programmed eeprom image in the system; hence this is only an alert to provide the eeprom. workaround: ensure that the platform contains a pre-pr ogrammed eeprom with valid vid/did before powering up the system . status: no fix 75. gbe: gbe interface transmit volt age level specification violation problem: the gbe 1000base-bx transmit buffers ha ve been designed to maximize performance and robustness over a variety of routing scenarios. as a result, the transmitter signaling voltage levels may exceed the maximum motherboard tx connector and rx connector peak-to-peak voltage specif ication of 1350 mv by about 5%. (see transmitter specification at tp-t (table 17), of picmg 3.1, r1.0 specification) implication: although this is a specification violatio n, it does not affect the functional operation of the interface. workaround: ensure that the signal routing length from tp-1 to tp-4 is greater than 10?. refer to intel? communications chipset 89xx seri es platform design guide (pdg) for maximum routing length. (see figure 2 ). status: no fix figure 2. 1000base-bx/fc-pi transmitter electrical specifications
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 35 errata?chipset 89xx series 76. usb: usb full/low speed port rese t or clear transaction translation (tt) buffer request problem: one or more full/low sp eed usb devices on the same rmh controller may be afftected if the devices are not suspended and either (a) software issues a port reset or (b) software issues a clear tt buffer request to a port executing a split full/low speed asynchronous out command. ? the small window of exposure for full-speed device is around 1.5 micro-seconds and around 12 micro-seconds for low-speed device implication: the affected port may stall or receive stale data for a newly arrived split transfer occurring at the time of the port reset or clear tt buffer request. note: this issue has only been observed in a synthetic test environment. workaround: none. status: no fix. 77. usb: usb rmh think time issue problem: the usb rmh think time may exceed it s declared value in the rmh hub descriptor register value of 8 full-speed bit times. implication: if the os usb driver fully subscrib es to usb microframe, ls/fs transactions may exceed the microframe boundary. note: no functional failures have been observed. workaround: none. status: no fix. 78. usb: usb rmh false disconnect issue problem: the pch may falsely detect a usb high-speed (hs) device disconnect if all of the following conditions are met: 1. the hs device is connected through th e rate matching hub (rmh) of teh pch?s ehci controller either directly or through a high-speed hub or series of high-speed hubs. 2. the device is resuming from selective suspend or port reset 3. the resume occurs within a narrow time window during the eop (end of packet) portion of the sof (start of frame) packet on the usb bus. implication: following the false disconnect, the hs device will be automatically re-enumerated. the system implication will depend on the cause of the resume event: ? if the resume event is a port reset, a second port reset will be automatically generated and the device re-enumerated. no end user impact is expected. ? if the resume event is a hardware or software initiated resume from selective suspend, the implication will be device an d software specific, which may result in anomalous system behavior.. note: if the hs device is a hub, then all of the devices behind the hub, independent of the device speed, may also be re-enumerated. workaround: none. status: no fix.
chipset 89xx series?specification changes intel ? communications chipset 89xx series specification update october 2012 36 order number: 328000-001US specification changes there are no specification changes in this revision of the specification update.
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 37 specification clarifications?chipset 89xx series specification clarifications 1. gbe: use of wake on lan together with manageability clarification: the wakeup filter control register (wufc) contains the notco bit, which affects the behavior of the wakeup functionality when manageability is in use. note that if manageability is not enabled, the value of notco has no effect. when notco contains the hardware default value of 0b, any received packet that matches the wakeup filters will wake the sy stem. this could cause unintended wakeups in certain situations. for example, if directed exact wakeup is used and the manageability shares the host?s mac address, ipmi packets that are intended for the bmc will wake the system, which might not be the intended behavior. when notco is set to 1b, any packet that passes the manageability filter, even if it also is copied to the host, is excluded from th e wakeup logic. this solves the previous problem since ipmi packets will not wake the system. however, with notco = 1b, broadcast packets, including broadcast magic packets, will not wake the system since they pass the manageability filters and are therefore excluded. the intel windows* drivers set notco by default. 2. gbe smbus: illegal stop condition clarification: it is important to prevent illegal st op conditions on the sm bus interface, even when resetting the management controller (mc). specifically, a stop condition should never be generated by the mc during the high clock phase of an ack cycle while reading packet data from gbe controller as part of a receive tco lan packet transaction. if this situation occurs, the controller replie s with a nack to all future commands until a power cycle. as a result, the smbus interface becomes inoperable. workaround: ensure that this illegal sequence does not occur, even during mc reset. effects of notco settings wol notco shared mac address unicast packet broadcast packet magic packet 0b - ok ok magic packet 1b y no wake no wake magic packet 1b n ok no wake directed exact 0b y wake even if mng packet. no way to talk to bmc without waking host. n/a directed exact 0b n ok n/a directed exact 1b - ok n/a
chipset 89xx series?specification clarifications intel ? communications chipset 89xx series specification update october 2012 38 order number: 328000-001US 3. gbe serdes: an_timeout only works when link partner idle clarification: the auto-negotiation timeout mech anism (pcs_lctl.an_timeo ut_en) only works if the serdes partner is sending idle code gr oups continuously for the duration of the timeout period, which is the usual case. however, if the partner is transmitting packets, an auto-negotiation timeout will not occur since auto-negotiation is restarted at the beginning of each packet. if the partner has an application that indefinitely transmits data despite the lack of any response, it is possible that a link will not be established. workaround: if this is a concern, the auto-negotiation timeout mechanism may be considered unreliable and an additional software mechanism could be used to disable auto- negotiation if sync is maintained without a link being established (pcs_lsts.sync_ok=1b and pcs_lsts.link_ok =0b) for an extended period of time.
intel ? communications chipset 89xx series october 2012 specification update order number: 328000 -001us 39 documentation changes?chipset 89xx series documentation changes there are no documentation changes in this revision of the specification update.

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